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10.2 Frame Transmit Procedure
A frame transmission comprises of two actions, a Frame Buffer write access and the
transmission of the Frame Buffer content. Both actions can be run in parallel if required
by critical protocol timing.
Figure 10-2 illustrates the Atmel AT86RF232 frame transmit procedure, when writing
and transmitting the frame consecutively. After a Frame Buffer write access, the frame
transmission is initiated by asserting pin 11 (SLP_TR) or writing command TX_START
to register bits TRX_CMD (register 0x02, TRX_STATE), while the radio transceiver is in
state PLL_ON or TX_ARET_ON. The completion of the transaction is indicated by
interrupt IRQ_3 (TRX_END).
Figure 10-2. Transaction between AT86RF232 and Microcontroller during Transmit.
Write frame data (Frame Buffer access)
Write TRX_CMD = TX_START, or assert pin 11 (SLP_TR)
IRQ_3 (TRX_END) issued
Read IRQ_STATUS register, pin 24 (IRQ) deasserted
Alternatively, a frame transmission can be started first, followed by the Frame Buffer
write access (PSDU data); refer to Figure 10-3 . This is applicable for time critical
applications.
Initiating a transmission, either by asserting pin 11 (SLP_TR) or command TX_START
to register bits TRX_CMD (register 0x02, TRX_STATE), the radio transceiver starts
transmitting the SHR, which is internally generated.
This first phase requires 16μs for PLL settling and 160 μs for SHR transmission. The
PHR must be available in the Frame Buffer before this time elapses. Furthermore the
SPI data rate must be higher than the PHY data rate to ensure that no Frame Buffer
under run occurs.
Figure 10-3. Time Optimized Frame Transmit Procedure.
Write TRX_CMD = TX_START, or assert pin 11 (SLP_TR)
Write frame data (Frame Buffer access)
IRQ_3 (TRX_END) issued
Read IRQ_STATUS register, pin 24 (IRQ) deasserted
124
AT86RF232
8321A – MCU Wireless – 10/11
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